Stacked dies are commonly used in Three-Dimensional (3D) integrated circuits. Through the stacking of dies, the footprint (form factor) of packages is reduced. In addition, the metal line routing in the dies is significantly simplified through the formation of stacked dies.
In some conventional applications, a plurality of dies is stacked to form a die stack, wherein the plurality of dies include Through-Substrate Vias (TSVs, sometimes known as through-silicon vias). The total count of the stacked dies may sometimes reach eight or more. When such a die stack is formed, a first die is first bonded onto a package substrate through flip-chip bonding, wherein solder regions/balls are reflowed to join the first die to the package substrate. A first underfill is dispensed into the gap between the first die and the package substrate. The first underfill is then cured. A test is then performed to ensure that the first die is connected to the package substrate properly, and that the first die and the package substrate function as desired.
Next, a second die is bonded onto the first die through flip-chip bonding, wherein solder regions/balls are reflowed to join the second die to the first die. A second underfill is dispensed into the gap between the second die and the first die. The second underfill is then cured. A test is then performed to ensure that the second die is connected to the first die and the package substrate correctly, and the first die, the second die, and the package substrate function as desired. Next, a third die is bonded onto the second die through the same process steps as for bonding the first die and the second die. The processes are repeated until all the dies are bonded.